The present invention relates to data receivers, especially for high-speed wired communications.
In high-speed data communications, especially those in which data is transmitted serially at rates greater than one gigabit per second (Gbs), wired communications become unreliable unless an equalizer is used to compensate the channel impairments. Two common types of equalizers are feed forward equalizers (“FFE”) and decision feedback equalizers (“DFE”). An FFE is used at a transmitter to pre-process the signal being transmitted in a way that compensates for the distorting effects of the transmission channel. In that way, the pre-processed signal arrives at the receiver with lower distortion. An example of an FFE is a multiple-tap finite impulse response (“FIR”) filter. A FIR is a device which digitally processes a serial digital signal for transmission by creating a coefficient-weighted sum of the instant datum of the digital signal together with one or more of the data preceding the instant datum and/or one or more of the data following the instant datum.
A DFE is used at a receiver to counter the effects of distortion present in a signal received from a transmission channel by subtracting scaled values of the preceding data captured by the receiver from the signal arriving at the receiver to capture the instant datum. A DFE is typically implemented as a set of taps through which variable coefficient values are used to scale the preceding data, the output of the taps being applied to a summer to perform the subtraction. An example of a DFE is described in U.S. Pat. No. 5,068,873 to Murakami. Typically, a DFE requires performance of an initial and/or occasional or periodic training sequences in which a transmitter and the receiver linked by a transmission channel are temporarily switched out of normal operation. In such training sequence, the transmitter is caused to transmit a data signal having a known sequence of data values for use at the receiver in characterizing the transmission channel. The results of that characterization are then used to set the tap coefficients of the DFE, typically via an algorithm which converges at high-speed. During normal operation, the DFE tracks variations in the distortion of the channel by monitoring an error signal. The error signal results from comparing the received signal and the reference signal using an algorithm that converges more slowly than that used to initially set the tap coefficients. As such, in normal operation, the DFE adaptively adjusts the tap coefficients in a way which “filters” out some of the variations in channel characteristics.
It is possible for wired communication systems to employ both an FFE at the transmitter and a DFE at the receiver to share the overall task of compensating for distortion in the link. A challenge for high-speed data receivers, especially high-speed serializer-deserializer (SerDes) units, is to simultaneously use both an FFE and a DFE simultaneously, such that the tap coefficients of the equalization devices at both ends of the channel are adjusted for optimal performance. In lower data-rate systems, e.g., systems in which the transmission rate is below 3 Gbs, FFEs having a few taps with preset, (i.e., permanently fixed) tap coefficients provide adequate performance while conserving power and area of the integrated circuit. However, such approach is inadequate for higher transmission rate systems. A serious obstacle exists to using a fixed-coefficient FFE at transmission rates above about 6 Gbs, due to greater variations in transmission characteristics from one channel to another channel, as well as greater variations in channel distortion.
High-speed serial data transmission is conventionally performed according to either a direct current (DC) coupling scheme or an alternating current (AC) coupling scheme, as shown in FIGS. 1 and 2. In a DC coupling scheme, as shown in FIG. 1, the transmitter is conductively connected to the receiver at DC as well as AC via a conductive medium, e.g., through one or more cards, cables, connectors, packages, and backplanes, etc. By contrast, as shown in FIG. 2, in an AC coupling scheme, capacitors 7 are placed in the path of signals between the transmitter and remote receiver to allow only AC signals to pass, while blocking the flow of current at DC between the transmitter and receiver. For this reason, the AC coupling capacitor is also known as a DC blocking capacitor. DC blocking capacitors can be provided on the same integrated circuit, i.e., the “chip” which contains the transmitter or the receiver, on the same package, or in a discrete device provided off the chip. The values of DC blocking capacitors typically range between about 10 nF and about 100 nF.
DC coupling is used only when transmitter and receiver are designed to operate at the same or similar signal common mode level (Vcm). FIG. 1 illustrates a serial data communication system including a transmitter 2, a receiver 3, and a pair of differential signal lines 4 and 5 which carry a data bit signal as a pair of differential signals between the transmitter 2 and the receiver 3. In such communication system, the common mode supply voltage Vtr to the receiver is set to the same level as the common mode supply voltage Vtt to the transmitter to avoid DC current flow between the transmitter and the receiver. The common mode supply voltage Vtt to the transmitter and the receiver operates as a reference level against which the signals arriving at the receiver from differential signal lines are distinguished.
In some DC coupled systems, the transmitter and receiver are designed to perform best when operated together as a matched pair, in which case the transmitter and receiver are said to be “compatible”. At minimum, DC coupling requires that the common mode level of the signal arriving at the receiver is within the range in which the receiver is designed to operate.
However, when the common mode level of the arriving signal lies outside the voltage range the receiver is designed to handle, the receiver cannot amplify the signal efficiently, and may recover data poorly. In such a case, and when the common mode level of the arriving signal is not known a priori, an AC coupling scheme is recommended instead of DC coupling. With reference to FIG. 2, in an AC coupled communication system, the receiver independently sets the common mode level of the received signal to a predetermined desirable level. In AC coupled systems, this is accomplished through the use of a supply voltage (“Vtr”) at the receiver to supply a DC current for maintaining the common mode signal level, in a manner which is independent from the supply voltage Vtt which is used to maintain the common mode signal level at the transmitter. As also shown in FIG. 2, a termination resistor 8, having a value matching the impedance of the transmission line, e.g., 50 ohm, is placed between a supply voltage Vtr and the data input signals.
Although an AC coupling scheme is advantageous for filtering out low-frequency noise and relaxing common mode demand, it requires that the data signal be transmitted according to a DC balanced code. Stated another way, the data signal arriving at the receiver must have an equal number of bits having the value “1” as the number of bits having the value “0” bits within a designated number of bits, in order to prevent common mode level from shifting. AC coupling also requires the data signal to transition frequently between “1”s and “0”s. In other words, the receiver cannot properly decode a signal in which a long consecutive string of “1s” or “0s” appears at the input to the receiver. Moreover, in systems in which only the data signal is transmitted but not the clock, it is difficult to recover the clock from the transmitted signal when the transmitted signal has long strings of either “1”s or “0”s. An “8b10b” code is an example of a DC balanced code. An 8b10b code guarantees that the data signal transitions at least twice for every 10 bits. However, a data signal transmitted via an 8b10b code requires 10 signal bits to transfer 8 bits of information, equivalent to 20% of bandwidth loss.
It would be desirable to provide serial data communication devices such as the SerDes transmitters and receivers described above, which can be utilized in multiple ways, in communication systems which are DC coupled as well as AC coupled, and in high-speed environments in which channel characteristics cannot be predicted a priori. However, heretofore, such flexibility has not been available in prior SerDes communication systems.
A block diagram illustrating the architecture of a prior art receiver complex 10 which has a targeted data transmission rate of between 2.5 and 3.2 Gbs is shown in FIG. 3. The receiver complex 10 has a front end interface unit FEI 11 at the input end of the receiver 12, which provides termination, ESD protection and circuitry for switching between modes for AC coupling and DC coupling. However, the FEI 11 provides only fixed termination impedances to the differential signal lines Dn and Dp arriving at the receiver 12 (and also to lines Dn′ and Dp′), making its design somewhat inflexible. The receiver complex 10 also includes a built-in-self-test (BIST) unit 16, which verifies operation upon initializing the receiver 12 by inputting a known data pattern into the receiver 12 and then verifying the outcome. The BIST unit 16 raises an “ERROR” flag 19 when the receiver 12 does not correctly receive the data.
The receiver 12 includes a pre-amplifier (A), a sample latch (B), and 2:1 demultiplexer (C), also referred to herein as a “demux”. The pre-amplifier A amplifies the incoming signals using a peaking device to extend the bandwidth. A pair of latches are provided in the sample latch B. Each takes a one-half rate clock signal (as compared to the recovered clock rate of the incoming data signal) from a clock and data recovery circuit 18 and uses it to sample and latch alternate bits from the signal data stream output by the pre-amplifier. Each of two latches in the demultiplexer C then uses a one-quarter rate clock signal to demultiplex the data and then feed the data into a shift register inside a deserializer 13. Eventually, the deserializer 13 outputs n bits of data in parallel to logic circuitry as Dout.
In the receiver complex 10 shown in FIG. 3, the clock data recovery (CDR) unit 18 extracts the clock from the incoming data stream using a phase rotator and a clock recovery algorithm. The CDR over-samples the differential data signals at the output of the pre-amplifier A and a digital circuit detects the time position of an edge (signal transition) of the differential data signals. The CDR determines a desirable time position at which to sample the differential data signals, as well as generates early and late signals if the detected edge of the data signals is not at its expected position. The early and late signals are used to control the output phase positions of the phase rotator in a feedback loop. However, no early signal and no late signal is generated if no edge is found.
The receiver complex 10 does not include a receiver equalization unit such as a DFE as described above. Despite the lack of a DFE, the receiver complex 10 still provides adequate performance at the above-mentioned 2.5-3.2 Gbs transmission rate. The receiver complex 10 is typically operated in conjunction with a transmitter having an FFE, as described above, in which the tap coefficients are fixed, not allowing the FFE coefficients to be adjusted by feedback over the actual transmission channel between the transmitter and receiver. Thus, in receiver complex 10, no provision has been made for transmitting, by any means, information for updating FFE coefficients of the transmitter from the receiver complex 10 back to the transmitter.
Accordingly, it would be desirable to provide a receiver complex and method for receiving signals in which the aforementioned limitations of the prior art are addressed.